Download Analog VLSI Neural Networks: A Special Issue of Analog by Yoshiyasu Takefuji (auth.), Yoshiyasu Takefuji (eds.) PDF

By Yoshiyasu Takefuji (auth.), Yoshiyasu Takefuji (eds.)

This publication brings jointly in a single position very important contributions and state of the art study within the speedily advancing sector of analog VLSI neural networks.
The publication serves as a very good reference, supplying insights into probably the most very important matters in analog VLSI neural networks learn efforts.

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Extra resources for Analog VLSI Neural Networks: A Special Issue of Analog Integrated Circuits and Signal Processing

Example text

A 32-stage winner-take-all test circuit was fabricated and tested. It was found capable of resolving input currents differing by 1-3 pA at total input levels of70-l40 /LA. 1 /LA. As a design target a figure of 5 pA for the current output of a naive weight has been used, so average resolution is to better than half the design current delivered by a single naive weight. Without added capacitance at the feedback node, the winner-take-all circuit with device geometries as designed has been found to permit overcharging of the feedback node in certain simulated worst-case scenarios.

A block diagram representing an overview of the proposed system is shown in figure 2. 2. Circuit Designs Many of the functions which are required to implement the model as described above may be achieved with well-known analog building blocks. In designing our circuitry, a current-mode approach was adopted for reasons of improved bandwidth and noise immunity. ) A settling time on the order of several hundred nanoseconds was targeted for feedforward excitatory or feedback inhibitory phases of network operation.

It is reset before each series of sniffs by discharging hold capacitors CH to Vtid or Vss ' It includes dynamic current mirrors to enhance the accuracy of the current copying function. During learning, we propose to exploit simple drainside hot-electron injection onto the floating gates of the weighting transistors through a gate oxide ofusual thickness. This obviates the need for EEPROM or other special processing to implement the floating-gate weights. A scheme for performing coactivity-based updating is outlined as follows.

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