By Douglas Perry, Harry Foster
Meant for layout engineers, this e-book introduces common verification ideas, compares them with formal verification suggestions, and gives directions for growing formal excessive point requirement. The authors talk about formal verification ideas for either utilized Boolean and sequential verification, formal estate checking, the method of constructing a proper attempt plan, and kingdom aid ideas. The appendices checklist ordinary PSL statements for top point requisites and related specifications laid out in process Verilog syntax.
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Extra info for Applied Formal Verification: For Digital Circuit Design
To check for conformance, we have two options: ♦ ♦ We can demonstrate that our design intent is preserved in our implementation, using dynamic approaches such as simulation. We can prove that our implementation satisfies the requirements of our specification, using formal verification. Simulation to Demonstrate Conformance To demonstrate conformance using simulation, we first create a testbench (or reference model), which captures the design requirements in a form suitable for simulation. In essence, the testbench becomes a refinement of our natural language specification during the verification process.
With the real hardware system it can be very difficult to capture the pin values at the correct time. With a simulation model any signal or pin can be examined at any time during the simulation. The simulation model allows the designer full control over the signal values in the design. At any time the designer can change the value of an internal signal. In the real design it is extremely difficult or impossible to modify the internal states of a design. The execution of the simulation model can be stopped at any time.
Observability versus Controllability Fundamental to the discussion of functional verification is an understanding of the concepts of controllability and observability. , a line of code or structure) within the design. Note that while in theory a simulation testbench has high controllability of its input ports for the design under verification, testbenches generally have poor controllability over internal points. Observability, in contrast, is a measurement of the ability to observe the effects of a specific, internal, stimulated point.