By Dr. Mark Ingels, Professor Michiel Steyaert (auth.)
This ebook offers numerous circuits which are required for the total integration of an optical transmitter in normal CMOS. the most emphasis is put on high-speed receivers with a bitrate of as much as 1 Gb/s. the opportunity of together with the photodiode in a receiver is investigated and the issues encountered are mentioned. about the transmitter point, a CMOS LED driving force is defined. the ultimate bankruptcy addresses electric interference difficulties on a chip and proposes countermeasures. many of the circuits during this ebook have all been discovered and dimension effects are provided, paving the best way for unmarried chip communique platforms during which the optical interfaces are built-in at the comparable die because the electronic circuitry.
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Extra resources for Integrated CMOS Circuits for Optical Communications
Note that this noise current is thus directly added to the photocurrent, just as with the single resistor optical receiver of Sect. 2. Here, the resistor is however larger for the same bandwidth thanks to the transimpedance structure. In optical communication systems, where bandwidth considerations require a large gm and limit the value of Rj , the resistor's noise is dominant at low frequencies, while the amplifier's noise becomes the largest at the higher frequencies. Minimal Input Referred Current Noise To achieve a maximal sensitivity of the receiver, the input referred current noise must be minimized.
3 gm This total output noise is compared with the output signal's power. This actually depends on the spectrum of the data signal and by this on the data coding scheme. 49) the squared RMS-value of the optical input current. 6 Noise Aspects ofthe Transimpedance Amplifier 35 tivity of the receiver corresponds with a maximal signal-to-noise ratio (SNR) at the output, which is given by: SNR = 10 . 51) - CGS X NCdiode is substituted, together with Eqs. 41), into Eq. 50). To derive the optimal C GS to Cdiode ratio, the right hand side of this equation is differentiated to X N and the result is solved to zero.
MIO). The length of those transistors is not minimal to provide a sufficiently large output impedance. The last PMOS transistor in the chain (MIO) is ten times larger than the others to permit a large signal swing in the last stage. To avoid oscillations due to the local feedback paths via the drain-gate capacitances of the current sources, a separate current reference is used for M 7 • This also augments the testability of the circuit. As the voltages at the drains of transistors M6 and M8 are in phase, their reference voltage is not split.